![]() Proposed 7T writes “1” through one NMOS and writes “0” using two NMOS pass transistors. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 µW at 0.35 V.Ī novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Data is held down to 0.325 V with 2.53 µW standby power. Measured read and write functionality is demonstrated with VDD down to 0.35 V (~100 mV lower than the threshold voltage). The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. ICIRCUIT RESIZE FREEThis paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). In addition, the average total power consumption for object detection and tracking which includes writing, read and hold power is 1.63× and 1.45× lesser than C6T and RD8T SRAM at 0.3V VDD. The proposed object detection and tracking method are based on macroblock resizing, which demonstrates an accuracy rate of 96.5%. This, in turn, minimizes the complexity of the algorithm and reduces the memory requirement for tracking. A quadtree based approach is employed to diminish the bounding box and to reduce the computations for fast and low power object tracking. Further, a fast, reliable, less memory usage object tracking algorithm and implementation of its memory block using ULP 8T SRAM is proposed. Moreover, the WSNM, WTP, and Ion/Ioff values are improved by 6.67%, 7.14%, and 68× as compared to RD-8T SRAM, respectively, at 0.3V VDD. Additionally, write static noise margin (WSNM), write trip point (WTP), read dynamic noise margin (RDNM) and Ion/Ioff ratio are also improved by 7.1%, 43%, 7.4%, and 74× than conventional 6T SRAM, respectively, at 0.3V VDD. It is observed that the leakage power is reduced to 82× (times) and 75× as compared to the conventional 6T SRAM and read decoupled (RD)-8T SRAM, respectively, at 300mV VDD. The proposed SRAM shows better results as compared to conventional SRAMs in terms of leakage power, write static noise margin, write-ability, read margin and Ion/Ioff. In this paper, an ultra-low power (ULP) 8T static random access memory (SRAM) is proposed. ![]()
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